PLL (phase locked loop) design engineer |
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Location: |
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E_mail:jobs@comlent.com |
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Posting Date:2009-03-13 |
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ESSENTIAL FUNCTION / RESPONSIBILITIES: |
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RFIC design mainly on PLL System:
- Plan, analyze, design, simulate, verify PLLs for wireless applications
- Providing recommendations on design, layout and test methodologies
- Integer/Fractional PLL system simulation, design and development
- Assist in development of production test
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QUALIFICATIONS / REQUIREMENTS: |
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Person Specification:
- MSEE or PhD in EE, plus at least 2 years of hands-on PLL design experience with a good track record
- In-depth understanding of phase noise mechanism in a PLL system, sigma-delta theory
- Experience in spur compensation, current matching, integrated LPF technique, noise shaping etc. is necessary
- Strong RFIC design skills, hands-on testing and diagnostics-related RF measurement experience and familiarity with CAD tools including Cadence Spectre, SpectreRF, Virtuso etc
- Experience with Matlab and/or Simulink, VerilogA coding, etc. is a plus
- Experience in taking an IC through design, layout, evaluation, and release to production
- Outstanding communication skills
- Self-motivated attitude and excellent team spirit
- Strong problem solving skills
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